IEEE

Designing and Implementation of 32-bit 5 stage Pipelined MIPS based RISC Processor Capable of Resolving Data Hazards

Abstract: The main objective is to design and implement a 5-stage pipelined 32-bit High performance RISC Processor with MIPS architecture which is also capable in detecting and resolving Data Hazards.
GitHub

data load tool (dlt) — the open-source Python library that automates all your tedious data loading tasks

dlt supports Python 3.9 through Python 3.14. Note that some optional extras are not yet available for Python 3.14, so support for this version is considered experimental. dlt is an open-source Python ...
IEEE

Reinforcement Learning based Load Balancing for Data Center Networks

Abstract: Data center networks are designed with multi-rooted topologies to provide the large bisection bandwidth. These topologies provide high path diversity and need a load balancing algorithm to ...