IEEE

VLSID 2025: Catalyzing AI-Driven VLSI and Semiconductor Innovation in India [Conference Reports]

Abstract: Provides society information that may include news, reviews or technical notes that should be of interest to practitioners and researchers.
IEEE

Ongoing Evolution of DRAM Scaling via Third Dimension -Vertically Stacked DRAM

Abstract: For the past decades, the density of DRAM has been remarkably increased by making access transistors and capacitors smaller in size per unit area. However, shrinking devices far beyond the ...
IEEE

An energy-efficient memory-based high-throughput VLSI architecture for convolutional networks

Abstract: In this paper, an energy efficient, memory-intensive, and high throughput VLSI architecture is proposed for convolutional networks (C-Net) by employing compute memory (CM) [1], where ...
IEEE

Comparison of Various Adders and their VLSI Implementation

Abstract: It is profoundly accepted that the main processing unit of any device capable of carrying out computations is the Central Processing Unit (CPU) and the one of the most fundamental and ...
IEEE

An Overview of Low-Power VLSI Design Methods for CMOS and CNTFET-Based Circuits

Abstract: Currently, the power consumption is one of the major concerns in VLSI circuit design based on CMOS (Complementary Metal Oxide Semiconductor) and CNTFET (Carbon Nano Tube Field Effect ...
IEEE

Heterogeneous Integration of BEOL Logic and Memory in a Commercial Foundry: Multi-Tier Complementary Carbon Nanotube Logic and Resistive RAM at a 130 nm node

Abstract: The inevitable slowing of two-dimensional scaling is motivating efforts to continue scaling along a new physical axis: the 3 rd dimension. Here we report back-end-of-line (BEOL) integration ...
IEEE

An energy-efficient VLSI architecture for pattern recognition via deep embedding of computation in SRAM

Abstract: In this paper, we propose the concept of compute memory, where computation is deeply embedded into the memory (SRAM). This deep embedding enables multi-row read access and analog signal ...
IEEE

A New Hardware-Efficient VLSI-Architecture of GoogLeNet CNN-Model Based Hardware Accelerator for Edge Computing Applications

Abstract: In the current trend, deep neural network (DNN) models that use only one type of convolution filters (mostly 3×3 convolution) are widely adopted for the hardware implementation. However, ...
IEEE

Low power VLSI circuits design strategies and methodologies: A literature review

Abstract: Researchers stare at the design of low power devices as they are ruling the today's electronics industries. In VLSI circuits, power dissipation is a critical design parameter as it plays a ...
IEEE

High-Throughput VLSI Architecture for GRAND Markov Order

Abstract: Guessing Random Additive Noise Decoding (GRAND) is a recently proposed Maximum Likelihood (ML) decoding technique. Irrespective of the structure of the ...
IEEE

An efficient VLSI architecture for data encryption standard and its FPGA implementation

Abstract: To achieve the goal of secure communication, cryptography is an essential operation. Many applications, including health-monitoring and biometric data based recognition system, need ...
IEEE

An Open-Source Constraints-Driven General Partitioning Multi-Tool for VLSI Physical Design

Abstract: With the increasing complexity of IC products, large-scale designs must be efficiently partitioned into multiple blocks, tiles, or devices for concurrent backend place-and-route (P&R) ...